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CXP971000 CMOS 16-bit Single Chip Microcomputer Description The CXP971000 is a CMOS 16-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP972032/973032/973064. Piggy/ evaluation type 100 pin PQFP (Ceramic) Features (LQFP supported) (QFP supported) * An efficient instruction set as a controller - Direct addressing, numerous abbreviated forms, multiplication and division instructions * Instruction sets for C language and RTOS - Highly quadratic instruction system, general-purpose register of eight 16-bit x 16-bank configuration * Minimum instruction cycle time 50ns at 40MHz operation (2.7 to 3.6V) * Incorporated EPROM CXP27V1000K * Incorporated RAM capacity 23.5K bytes * Peripheral functions -- A/D converter 8-bit 12-analog input, successive approximation system, 3-stage FIFO (Conversion time: 1.55s at 40MHz) -- Serial interface Asynchronous serial interface (UART) 128-byte buffer RAM, 3 channels -- I2C bus interface 64-byte buffer RAM (supports master/slave and automatic transfer mode) -- Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels, watchdog timer -- PWM output circuit 14-bit PWM, 4 channels (2-channel of binary output switch function by PPG) -- Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel -- Remote control receive circuit 8-bit pulse measurement counter, 10-stage FIFO -- Parallel interface External register interface (8-bit parallel bus), 4-chip select * Interruption 33 factors, 33 vectors, multi-interruption and priority selection possible * Standby mode Sleep/stop * Package 100-pin Ceramic PQFP * Mask ROM CXP972032/973032/973064 * FLASH EEPROM incorporated type CXP973F064 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E00423A08-PS CXP971000 Pin Assignment in Piggyback Mode (Top View) 100-pin QFP package PB1/PPO01/A9 PB0/PPO00/A8 PH6/XWR PH4/RMC PH7/XRD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PH1/SCL PH2/RxD PH3/TxD PA7/A7 PA6/A6 PA5/A5 PA4/A4 PA3/A3 PA2/A2 PA1/A1 PA0/A0 PH5 VDD VSS NC PB2/PPO02/A10 PB3/PPO03/A11 PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5 PE6/INT6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A11 A12 D7 D6 D5 D4 D3 D2 D1 D0 Vss A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD CE NC D15 D14 D13 D12 D11 D10 D9 D8 Vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PH0/SDA PK6 PK5 PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AVDD AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2 PI2/SO2 PI1/SI2 PI0/SCS2 PG7/SCK0 PG6/SO0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PF0/EC0 PF1/EC2 PF2/SCS1/NMI PF3/SI1 PF4/SO1 PF5/SCK1 PF6/T1 PE7/INT7/CINT PF7/T2 RST PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/SCS0 Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND. 3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. -2- PG5/SI0 VSS XTAL EXTAL VDD CXP971000 Pin Assignment in Evaluator Mode (Top View) 100-pin QFP package PB1/PPO01/A9 PB0/PPO00/A8 PH6/XWR PH4/RMC PH7/XRD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PH1/SCL PH2/RxD PH3/TxD PA7/A7 PA6/A6 PA5/A5 PA4/A4 PA3/A3 PA2/A2 PA1/A1 PA0/A0 PH5 VDD VSS NC PB2/PPO02/A10 PB3/PPO03/A11 PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5 PE6/INT6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD AD11 AD12 I/T MON ERST C1 C2 QS0 QS1 QS2 Vss A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD E/P ST0 ST1 ST2 ST3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 PH0/SDA PK6 PK5 PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AVDD AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2 PI2/SO2 PI1/SI2 PI0/SCS2 PG7/SCK0 PG6/SO0 WTACK 65 JRQH JRQL ENMI MS Vss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PF0/EC0 PF1/EC2 PF2/SCS1/NMI PF3/SI1 PF4/SO1 PF5/SCK1 PF6/T1 PE7/INT7/CINT PF7/T2 RST PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/SCS0 Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND. 3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. -3- PG5/SI0 XTAL EXTAL VDD VSS CXP971000 Pin Assignment in Piggyback Mode (Top View) 100-pin LQFP package PB2/PPO02/A10 PB3/PPO03/A11 PB1/PPO01/A9 PB0/PPO00/A8 PH6/XWR PH4/RMC PH7/XRD PA7/A7 PA6/A6 PA5/A5 PA4/A4 PA3/A3 PA2/A2 PA1/A1 PA0/A0 PH1/SCL PH2/RxD PH3/TxD PH5 PH0/SDA PK6 VSS VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PK4 PK3 PK2 PK1 PK0 AVD AVR AVS PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PI7/ PI6/ PI5/ PI4/ Vss PI3/ PI2/ PI1/ PI0/ PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A11 A12 D7 D6 D5 D4 D3 D2 D1 D0 Vss A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD CE NC D15 D14 D13 D12 D11 D10 D9 D8 Vss NC PK5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PF0/EC0 PF1/EC2 PF2/SCS1/NMI PF3/SI1 PF4/SO1 PF5/SCK1 PF6/T1 PE7/INT7/CINT PF7/T2 RST PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/SCS0 PG5/SI0 XTAL EXTAL VDD VSS PE4/INT4 PE5/INT5 Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND. 3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. -4- PE6/INT6 PG6/SO0 CXP971000 Pin Assignment in Evaluator Mode (Top View) 100-pin LQFP package PB2/PPO02/A10 PB3/PPO03/A11 PB1/PPO01/A9 PB0/PPO00/A8 PH6/XWR PH4/RMC PH7/XRD PA7/A7 PA6/A6 PA5/A5 PA4/A4 PA3/A3 PA2/A2 PA1/A1 PA0/A0 PH1/SCL PH2/RxD PH3/TxD PH5 PH0/SDA PK6 VSS VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PK4 PK3 PK2 PK1 PK0 AVD AVR AVS PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PI7/ PI6/ PI5/ PI4/ Vss PI3/ PI2/ PI1/ PI0/ PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15 PC0/PPO08 PC1/PPO09 PC2/PPO10 PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0 VSS PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19 PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD AD11 AD12 I/T MON ERST C1 C2 QS0 QS1 QS2 Vss A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD E/P ST0 ST1 ST2 ST3 WTACK JRQH JRQL ENMI MS Vss NC PK5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PF0/EC0 PF1/EC2 PE7/INT7/CINT PF2/SCS1/NMI PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/SCS0 PF4/SO1 PF5/SCK1 PG5/SI0 VSS XTAL EXTAL PF3/SI1 PF6/T1 PF7/T2 RST VDD PE4/INT4 PE5/INT5 Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND. 3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. -5- PE6/INT6 PG6/SO0 CXP971000 EPROM Read Timing (Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V) Item Address data Input delay time Address data hold time Symbol Pins A0 to A23 D0 to D15 A0 to A23 D0 to D15 0 Min. Max. 50 Unit ns ns tACC tIH 0.8VDD A0 to A23 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D15 Product List Type Product name Package ROM capacity Reset pin pull-up resistor Piggy/evaluation chip CXP971000-U01Q 100-pin ceramic PQFP (QFP supported) CXP971000-U01R 100-pin ceramic PQFP (LQFP supported) EPROM 512K bytes Existent -6- CXP971000 Switching of Piggyback Mode and Evaluator Mode Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting to the connector of top of the chip. Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip. Piggyback mode Pin 1 marking 0 1 For lower bytes For upper bytes EPROM adaptor Chip LCC-type PROM Evaluator mode CPU probe Chip Notes on PK6 Usage FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings: 1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150k), and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load impedance. 2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output prior to software reset execution or connecting pull-up resistor is recommended. RST Normal operation PK6 Flash mode Keep PK6 above 0.7 VDD during this period. Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM incorporated type is used, above countermeasure should be performed. -7- CXP971000 Package Outline Unit: mm 100PIN PQFP(CERAMIC) 24.7 0.5 22.3 0.25 80 81 51 50 18.0 1.5 0.05 18.7 0.5 16.3 0.2 3.2 0.2 31 1 0.8 0.1 30 INDEX INDEX 3.57 0.36 0.5 0.25 + 0.05 0.15 - 0.02 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L04 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 4.9g -8- 8.6 MAX 0.3 0.08 100 13.9 0.65 0.05 CXP971000 100PIN PQFP(CERAMIC) 16.0 0.5 0.5 0.05 14.0 0.2 75 76 51 50 12.4 12.0 0.15 + 0.08 0.18 - 0.03 1.5 0.05 100 1 25 0.8 0.1 26 3.2 0.2 INDEX INDEX + 0.05 0.127 - 0.02 3.32 0.33 + 0.15 0.2 - 0.13 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L03 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 2.7g -9- 8.0 MAX Sony Corporation |
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